Memory circuit arrays positioned on semiconductor chips have become an important component common to VLSI circuits. Memory circuits rely upon storage of data in a memory array within a section of a chip designated for memory. The memory array is comprised of memory cells.
Memory circuits are of two basic types—volatile memory circuits and nonvolatile memory circuits. A nonvolatile memory circuit does not lose stored “bits” or information when the circuit loses power. For a volatile memory circuit, information is lost when the circuit loses power.
ROM or read-only memory is a basic type of nonvolatile memory. Data stored in ROM is a permanent part of the circuit. The ROM circuit provides precoded information to a user. One variation of ROM is an erasable programmable ROM, commonly referred to as EPROM. To create the erasable feature, a transistor, such as a memory MOS transistor, is selectively charged to impart data to the memory field. The memory field is programmed by a procedure of hot electron injection. The memory field may be re-programmed by draining off the charge, removing the chip from the circuit and imparting a new memory with an exterior source.
An improvement to EPROM is a memory circuit that can be reprogrammed while the chip is in a socket of a machine. This memory circuit, an EEPROM circuit, is prepared for reprogramming by draining charge and by charging the memory circuit in place. The EEPROM memory circuit is programmed and reprogrammed by hot electron injection.
Both EPROM and EEPROM comprise a large number of memory cells having electrically isolated gates, referred to as floating gates. Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by program and erase operations, respectively.
One other type of memory circuit, a FLASH circuit, is a form of EEPROM, which is a form of electronically erasable, programmable, read only memory. FLASH memory is based upon a one-transistor cell design but has a capacity for in-socket programming and erasure. FLASH memory is a type of nonvolatile memory. FLASH memory differs from EPROM and EEPROM in that erase programs are done in blocks.
One prior art memory circuit, illustrated in FIGS. 1(a) and 1(b), comprises a memory 184 with a memory array 198, control logic 194 and address logic 196, illustrated in prior art FIG. 1(b). The address logic 196 receives an address from an external system, such as a microprocessor. The control logic 194 receives external commands to store or to retrieve data to or from the memory array 198 at cell location(s) provided to the address logic 196 by the external system. Subsequently, the data associated with cell location(s) is respectively transmitted to or received from the external system.
The memory 184 may be FLASH memory. The memory array 198 includes a plurality of FLASH cells of each having a floating gate transistor such as storage transistor 182 of FIG. 1(a). The storage transistor 182 comprises two gates, a floating gate stack 170 and a control gate stack 172, an active source region 152a and an active drain region 152b and a channel 162 also formed in the semiconductor 168. Both the floating gate stack 170 and the control gate stack 172 are formed by conductors 122 and 124 and gate oxides 144 and 146.
Nonvolatile memory storage in a circuit requires a permanent storage of charge in the floating gate stack region of the memory circuit. Nonvolatile memory storage in a memory circuit such as an EEPROM or a FLASH memory circuit is made possible by materials used in the gate region, including materials added by doping and by structural design of the gate region. These materials include silicon of a wafer supporting the circuit and silicon oxide formed during gate fabrication.
FLASH memory is especially sensitive to degradation effects due to a substantial number of hot electrons generated in each memory cell during flash memory cycling. Specifically, during an operation of programming a memory cell, a positive programming voltage is applied to the control gate stack 172. This positive programming voltage attracts electrons from the semiconductor 168 which is a p-type substrate and causes them to accumulate at the surface of channel region 162. A voltage on drain 152b is increased and the source 152a is connected to ground. As the drain-to-source voltage increases, electrons flow from the source 152a to drain 152b via the channel region 162. As electrons travel toward drain 152b they acquire substantially large kinetic energy and are referred to as hot electrons. The hot electrons are injected through the oxide layer 146 and are stored on floating gate stack 170.
FLASH memory cycling occurs when the FLASH memory is repeatedly programmed and erased. With FLASH memory cycling, a significant number of substrate hot electrons are trapped within an insulating gate oxide layer 146, such as is shown in the prior art FLASH circuit in FIG. 1(a), that separates a drain region 152a from the floating gate stack 170. The greater the number of cycles that a FLASH memory device is subjected to, the greater the number of carriers that become trapped in the gate oxide.
The trapping and accumulation of hot electrons starts a charging process. Gradually, as the charge on the floating gate increases, the electric field in oxide layer 144 decreases and eventually loses its capability of attracting any more of the hot electrons to the floating gate 170. At this point, the floating gate stack 170 is fully charged. The negative charge from the hot electrons collected in the floating gate stack 170 raises the cell's threshold voltage above a logic 1 voltage. If the voltage on control gate stack 172 is brought to a logic 1 during a read operation, the cell will barely turn on. Sense amplifiers are used in the memory to detect and amplify the state of the memory cell during a read operation. Thus, data is read from a memory cell based upon its “ON” characteristics.
Hot electron degradation effects have been observed in FLASH memories in two ways. Most noticeably, the erase/programming times for a given memory array are increased far beyond their normal limits. This phenomena is frequently referred to a “erasetime/programtime push-out.” This means that as the devices are repeatedly cycled, a greater amount of erase/program time must be allotted for each successive cycle in order to insure that the entire array is completely charged or discharged.
A second indication that degradation effects are manifested in a FLASH memory cell array is an excess charge loss which renders the memory devices unreliable. That is, even though the device is initially programmed to an “apparently” correct level, with time that programming level may drop below the limits of reliable operation. This “apparent” charge loss of the devices occurs after extensive program-erase cycles.
Several methods have been developed in attempts to reduce hot electron induced degradation. One method uses a lightly doped drain, LDD, positioned proximal to a highly doped region. The LDD spreads an electric field in an attempt to prevent the hot electrons from gaining sufficient energy to break the silicon-hydrogen bonds. The use of an LDD reduces but does not eliminate the effects of hot electron induced degradation. Furthermore, the use of an LDD may further degrade the transistor by creating higher resistance than desired.
Another method is described in an article by F. C. Hsu et al., “Effect of Final Annealing on Hot-Electron-Induced MOSFET Degradation,” IEEE Device Letters, vol. ed1–6, No. 7, July 1985. A metal oxide semiconductor field effect transistor (MOSFET) as used herein refers to a field-effect transistor containing a metal gate over thermal oxide over silicon. The method described in Hsu et al. for reducing the effects of hot electron induced degradation has included a use of a nitrogen ambient rather than a hydrogen ambient to perform a final anneal in a post-metallization procedure in order to reduce the amount of hydrogen available to bond with silicon. Although the use of the nitrogen ambient reduced the amount of hydrogen available to bond with silicon, it was difficult to eliminate hydrogen entirely, since many of the procedures employed to fabricate a MOSFET are hydrogen-dependent. Thus, while the use of nitrogen ambient reduced the amount of hydrogen present, the use did not eliminate hydrogen nor the problems caused by hot electron induced degradation.
Electrons are removed from the floating gate to erase the memory cell. Many memories, including FLASH memories, use Fowler-Nordheim (FN) tunneling to erase a memory cell. The erase program is accomplished by electrically floating the drain, grounding the source, and applying a high negative voltage to the control gate. This creates an electric field across the gate oxide and forces electrons off the floating gate. The electrons then tunnel through the gate oxide.
One of the difficulties with FLASH memories has been with the erase operation using Fowler-Nordheim tunneling. The erase operation requires high voltages, and is relatively slow. Further, an erratic over erase can be induced as a result of the very high erase voltages used. These very high erase voltages are a fundamental problem arising from the high electron affinity of bulk silicon or large grain polysilicon particles used as the floating gate. The high erase voltages create a very high tunneling barrier. Even with high negative voltages applied to the gate, a large tunneling distance is experienced with a very low tunneling probability for electrons attempting to leave the floating gate. This results in long erase times because the net flux of electrons leaving the gate is low. Thus, the tunneling current discharging the gate is low.
Other phenomena result as a consequence of this very high negative voltage. One phenomenon is hole injection. Hole injection into the oxide is experienced which can result in erratic over erase, damage to the gate oxide itself and the introduction of trapping states.
A reference of K. Hess et al., IEEE Transactions on Electron Devices, vol. 45, No. 2, February 1998, entitled, “Giant Isotope Effect in Hot Electron Degradation of Metal Oxide Silicon Devices,” at pp. 406 to 416, describes a giant isotope effect of hot electron degradation. The effect was observed in integrated circuits of a complementary metal oxide silicon (CMOS) type. To study this effect, the authors passivated silicon wafers with deuterium instead of hydrogen.
The authors observed that the desorption efficiency for deuterium from silicon was about a factor of fifty lower than for hydrogen for energies above about 5 eV. The authors concluded that hydrogen migration played some role in mechanisms responsible for gate oxide wear-out. In particular, the authors concluded that a large deuterium content at a silicon wafer interface could be correlated to an improvement in transistor lifetime for some types of transistors. The authors attributed the longer lifetime to minimized damage occurring during a single event of hot electron injection.
With hot electron injection, the steady state of hydrogen within a silicon dioxide film is disrupted because the energy from the injection ionizes the hydrogen to H+ions. It is believed that electrons from the hot electron injection excite or collide with hydrogen that is bound to silicon or polysilicon at the Si/SiO2 interface. A collection of H+ ions drift to a memory storage area of the memory circuit, such as a floating gate, and combine with stored electrons.
The stored electrons are ordered within fields so as to “hold” nonvolatile memory within the circuit. Once hydronium ions are combined with electrons, hydrogen gas is formed and data within the memory is destroyed. As a consequence, the transistor is degraded.